Techniques to embed SiGe source/drain regions have been used for CMOS devices to increase compressive stress in the channel region of PMOS devices to improve device performance by improving hole mobility. In such process flows, following gate stack and source/drain extension formation, a cavity is formed in the source/drain regions of the PMOS device. Cavity formation is generally accomplished by a multi-step dry etch process, followed by a wet etch process.
The first dry etch step is a first anisotropic dry etch used to etch through a deposited hardmask layer (e.g., silicon nitride) to begin etching of a cavity in the substrate (e.g., silicon), followed by an isotropic dry lateral etch (dry lateral etch) that expands the cavity including laterally toward the PMOS transistor channel, followed by a second anisotropic dry etch to define the bottom wall of the cavity.
The multi-step dry etch is generally followed by a wet crystallographic etch which forms a “diamond-shaped” cavity. The wet etchant for the crystallographic etch has crystal orientation selectivity to the substrate material, such as an etchant comprising tetramethyl ammonium hydroxide (TMAH), which is used to etch the substrate beginning with the U-shaped recesses provided by the multi-step dry etch processing. During the wet crystallographic etching process, the etch rate of the <111> crystal orientation is less than that of other crystal orientations such as <100>. As a result, the U-shaped recess becomes a diamond-shaped recess.
FIG. 1A is a depiction showing an in-process PMOS transistor just prior to the formation of SiGe (silicon germanium) source and drain diffusions. The PMOS transistor is shown having a gate stack including a gate electrode 104 on a substrate 102 such as silicon, with a sidewall spacer 116 on the walls of the gate stack and a hard mask layer (e.g., silicon nitride) 106 on the gate electrode 104. P-type source and drain extensions 110 and n-type halo or pockets 112 are formed self aligned to an offset spacer 108 dielectric such as silicon dioxide or silicon nitride. The p-type extensions 110 electrically connect the PMOS transistor channel to the deep source drains to which contacts are formed. The n-type pockets 112 increase the doping in the PMOS transistor channel 114 and set the PMOS transistor turn on voltage (vtp).
FIG. 1B shows the PMOS transistor immediately after completing multi-step dry cavity etch processing. Typically the first dry etch step is a first anisotropic dry etch used to etch through a deposited hardmask layer (eg. silicon nitride) and to begin etching a cavity into the substrate 102. This is followed by an isotropic dry lateral etch step that expands the cavity laterally 118 toward the PMOS transistor channel 114. This etch is typically followed by a second anisotropic dry etch to define the bottom wall of the cavity 120.
FIG. 1C shows a depiction of an in-process PMOS transistor after the wet crystallographic cavity etch forms diamond-shaped recesses 122. The C2G (cavity to gate space) is the distance from the edge of the cavity to the edge of the transistor gate.
Following the wet crystallographic etch, boron doped SiGe is grown epitaxially in the diamond-shaped recesses to form the PMOS embedded SiGe source/drain regions. The embedded SiGe regions are spaced close enough to the outer edge of the PMOS transistor channel so that they impart a high amount of compressive stress to the channel. However, the SiGe regions are not too close to the outer edge of the PMOS transistor channel so that dopant diffusion from the in-situ doping in the SiGe runs into the PMOS channel and alters the PMOS threshold voltage (vtp).
Integrated circuits often require PMOS transistors with a low turn on voltage (LVPMOS) for high performance circuits in addition to the core PMOS transistors. Typically one pattern and implantation step is used to set the vt of the core PMOS transistors and a second pattern and implantation step is used to set the lower vtp of the LVPMOS transistors.